(VRV32C Load and Store Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I4
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I12
sVwid_order
p12
I12
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_C.LWSP
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I3
sg8
g17
sVtag
p23
VVP_IP009_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F009_S000_I000
p34
sVdescription
p35
Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 16.3
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rd registers are used.
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_ISA_F009_S000_I001
p62
sg35
Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number
p63
sg37
VUnprivileged ISA\u000aChapter 16.3
p64
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled
p65
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
a(V002
p71
g1
(g29
g3
Ntp72
Rp73
(dp74
g8
V002
p75
sg23
VVP_ISA_F009_S000_I002
p76
sg35
Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number
p77
sg37
VUnprivileged ISA\u000aChapter 16.3
p78
sg39
VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled
p79
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp80
sg15
(lp81
sg52
(lp82
sg13
(dp83
g55
I0
ssbtp84
asVrfu_list_1
p85
(lp86
sg52
(lp87
sg13
(dp88
sbtp89
a(V001_C.SWSP
p90
g1
(g18
g3
Ntp91
Rp92
(dp93
g22
I2
sg8
g90
sg23
VVP_IP009_P001
p94
sg25
(dp95
sg12
I1
sg15
(lp96
(V000
p97
g1
(g29
g3
Ntp98
Rp99
(dp100
g8
V000
p101
sg23
VVP_ISA_F009_S001_I000
p102
sg35
Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number
p103
sg37
VUnprivileged ISA\u000aChapter 16.3
p104
sg39
VRegister operands:\u000a\u000aAll possible rs2 registers are used.
p105
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp106
sg15
(lp107
sg52
(lp108
sg13
(dp109
g55
I0
ssbtp110
a(V001
p111
g1
(g29
g3
Ntp112
Rp113
(dp114
g8
V001
p115
sg23
VVP_ISA_F009_S001_I001
p116
sg35
Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number
p117
sg37
VUnprivileged ISA\u000aChapter 16.3
p118
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled
p119
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp120
sg15
(lp121
sg52
(lp122
sg13
(dp123
g55
I0
ssbtp124
asg85
(lp125
sg52
(lp126
sg13
(dp127
sbtp128
a(V002_C.LW
p129
g1
(g18
g3
Ntp130
Rp131
(dp132
g22
I3
sg8
g129
sg23
VVP_IP009_P002
p133
sg25
(dp134
sg12
I2
sg15
(lp135
(V000
p136
g1
(g29
g3
Ntp137
Rp138
(dp139
g8
V000
p140
sg23
VVP_ISA_F009_S002_I000
p141
sg35
Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1')
p142
sg37
VUnprivileged ISA\u000aChapter 16.3
p143
sg39
VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used
p144
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp145
sg15
(lp146
sg52
(lp147
sg13
(dp148
g55
I0
ssbtp149
a(V001
p150
g1
(g29
g3
Ntp151
Rp152
(dp153
g8
V001
p154
sg23
VVP_ISA_F009_S002_I001
p155
sg35
Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1')
p156
sg37
VUnprivileged ISA\u000aChapter 16.3
p157
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled
p158
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp159
sg15
(lp160
sg52
(lp161
sg13
(dp162
g55
I0
ssbtp163
a(V002
p164
g1
(g29
g3
Ntp165
Rp166
(dp167
g8
V002
p168
sg23
VVP_ISA_F009_S002_I002
p169
sg35
Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1')
p170
sg37
VUnprivileged ISA\u000aChapter 16.3
p171
sg39
VOutput result:\u000a\u000ard` value is non-zero and zero\u000aAll bits of rd are toggled
p172
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp173
sg15
(lp174
sg52
(lp175
sg13
(dp176
g55
I0
ssbtp177
asg85
(lp178
sg52
(lp179
sg13
(dp180
sbtp181
a(V003_C.SW
p182
g1
(g18
g3
Ntp183
Rp184
(dp185
g22
I2
sg8
g182
sg23
VVP_IP009_P003
p186
sg25
(dp187
sg12
I3
sg15
(lp188
(V000
p189
g1
(g29
g3
Ntp190
Rp191
(dp192
g8
V000
p193
sg23
VVP_ISA_F009_S003_I000
p194
sg35
Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1').
p195
sg37
VUnprivileged ISA\u000aChapter 16.3
p196
sg39
VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used
p197
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp198
sg15
(lp199
sg52
(lp200
sg13
(dp201
g55
I0
ssbtp202
a(V001
p203
g1
(g29
g3
Ntp204
Rp205
(dp206
g8
V001
p207
sg23
VVP_ISA_F009_S003_I001
p208
sg35
Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1').
p209
sg37
VUnprivileged ISA\u000aChapter 16.3
p210
sg39
VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled\u000aAll bits of rs2` are toggled
p211
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp212
sg15
(lp213
sg52
(lp214
sg13
(dp215
g55
I0
ssbtp216
asg85
(lp217
sg52
(lp218
sg13
(dp219
sbtp220
asVrfu_list_0
p221
(lp222
sg85
(lp223
sVvptool_gitrev
p224
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p225
sVio_fmt_gitrev
p226
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p227
sVconfig_gitrev
p228
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p229
sVymlcfg_gitrev
p230
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p231
sbtp232
.